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INTEGRATED CIRCUITS
74LV109 Dual JK flip-flop with set and reset; positive-edge trigger
Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 Apr 20
Philips Semiconductors
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
FEATURES
* Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Output capability: standard * ICC category: flip-flops
Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LV109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr =tf 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VI = GND to VCC
1
CONDITIONS
TYPICAL 14 12 12 77 3.5 20
UNIT ns MHz pF pF
CL = 15 pF; VCC = 3.3 V
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV109 N 74LV109 D 74LV109 DB 74LV109 PW NORTH AMERICA 74LV109 N 74LV109 D 74LV109 DB 74LV109PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
PIN CONFIGURATION
1R D 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC 2R 2J 2K 2CP 2S D D
PIN DESCRIPTION
PIN NUMBER 1, 15 2, 14, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 SYMBOL 1RD, 2RD 1J, 2J, 1K, 2K 1CP, 2CP 1SD, 2SD 1Q, 2Q 1Q, 2Q GND VCC FUNCTION Asynchronous reset input (active LOW) Synchronous inputs; flip-flops 1 and 2 Clock input (LOW-to-HIGH, edge-triggered) Asynchronous set inputs (active LOW) True flip-flop outputs Complement flip-flop outputs Ground (0 V) Positive supply voltage 853-1986 19255
1J 1K 1CP 1S D 1Q 1Q GND
2Q 2Q
SV00517
1998 Apr 20
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
LOGIC SYMBOL (IEEE/IEC)
5 S 2 1J 4 C1 3 1K 1 R 15 R 7 13 1K 12 C1 9 6 14 1J 11 S 10
FUNCTIONAL DIAGRAM
5 1SD 1J SD J Q FF1 Q RD 1 1RD 11 2SD SD (b) 14 2J J Q FF2 Q RD 2Q 9 2Q 10 1Q 7 1Q 6
2
4 1CP CP 3 1K K
(a)
SV00519
12 2CP
CP
LOGIC SYMBOL
5 11 1S D 2S D
13 2K K
15 2RD
SV00520
2 1J 14 2J 4 1CP 12 2CP 3 1K 13 2K
J Q
1Q 6 2Q 10
CP 1Q 7 K Q 2Q 9
1R D 2R D 1 15
SV00518
LOGIC DIAGRAM
K C C C C Q
Q J C S C C C
R C C
CP
SV00521
1998 Apr 20
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
FUNCTION TABLE
INPUTS OPERATING MODES Asynchronous set Asynchronous reset Undetermined Toggle Load "0" (reset) Load "1" (set) Hold "no change" nSD L H L H H H H nRD H L L H H H H nCP X X X nJ X X X h l h l nK X X X l l h h nQ H L H q L H q OUTPUTS nQ L H H q H L q
NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. X = don't care = LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V PARAMETER DC supply voltage CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - TYP. 3.3 - - MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V C ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with - standard outputs Storage temperature range Power dissipation per package - plastic DIL - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12 mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +4.6 20 50 25 50 -65 to +150 750 500 400 UNIT V mA mA mA mA C mW
NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 20
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V VIL LOW l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V; VI = VIH or VIL; -IO = 100A VO OH HIGH level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; -IO = 100A VCC = 2.7 V; VI = VIH or VIL; -IO = 100A VCC = 3.0 V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; -IO = 6mA VCC = 1.2 V; VI = VIH or VIL; IO = 100A VO OL LOW level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; IO = 100A VCC = 2.7 V; VI = VIH or VIL; IO = 100A VCC = 3.0 V; VI = VIH or VIL; IO = 100A VOL LOW level output voltage; STANDARD outputs Input leakage current Quiescent supply current; flip-flops Additional quiescent supply current per input VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT
II ICC ICC
VCC = 3.6 V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V
1.0 20.0 500
1.0 80 850
A A A
NOTE: 1. All typical values are measured at Tamb = 25C.
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/tPLH Propagation delay g y nCP to nQ, nQ Figure 1 2.0 2.7 3.0 to 3.6 1.2 tPLH Propagation delay g y nSD to nQ Figure 2 2.0 2.7 3.0 to 3.6 MIN LIMITS -40 to +85 C TYP1 90 31 23 182 55 19 14 102 36 26 21 44 33 26 ns 58 43 34 70 51 41 ns MAX -40 to +125 C MIN MAX UNIT
1998 Apr 20
5
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER CONDITION VCC(V) 1.2 tPHL Propagation delay g y nSD to nQ Figure 2 2.0 2.7 3.0 to 3.6 1.2 tPHL Propagation delay g y nRD to nQ Figure 2 2.0 2.7 3.0 to 3.6 1.2 tPLH Propagation delay g y nRD to nQ Figure 2 2.0 2.7 3.0 to 3.6 2.0 tW Clock pulse width HIGH or LOW Figure 1 2.7 3.0 to 3.6 2.0 tW Set or reset pulse width HIGH or LOW Figure 2 2.7 3.0 to 3.6 1.2 trem Removal time nSD, nRD to nCP Figure 2 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time nJ, nK to CP Figure 1 2.0 2.7 3.0 to 3.6 1.2 th Hold time nJ, nK to nCP Figure 1 2.0 2.7 3.0 to 3.6 2.0 fmax Maximum clock ulse pulse frequency Figure 1 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V. 5 5 5 14 19 24 22 16 13 24 18 14 34 25 20 34 25 20 MIN LIMITS -40 to +85 C TYP1 75 26 19 172 75 26 19 152 70 24 18 132 12 9 72 9 6 52 35 12 9 72 30 10 8 62 -5 -2 -1 02 40 58 702 5 5 5 12 16 20 MHz ns 26 19 15 ns 29 21 17 ns 44 33 26 41 30 24 41 30 24 ns ns 54 40 32 ns 46 36 29 60 44 35 ns 46 36 29 60 44 35 ns MAX -40 to +125 C MIN MAX UNIT
WAVEFORM
1998 Apr 20
6
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V; VM = 0.5 x VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load.
VI nJ, nK INPUT GND
TEST CIRCUIT
VCC
VI VM t su t su 1/f max PULSE GENERATOR RT th D.U.T.
VO
50pF CL th
RL = 1k
VI nCP INPUT GND
Test Circuit for switching times
VM tW t PHL t PLH
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VM TEST tPLH/tPHL VCC < 2.7V 2.7-3.6V VM VI VCC 2.7V
VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL t PLH
SV00901
Figure 3. Load circuitry for switching times.
t PHL
The shaded areas indicate when the input is permitted to change for predictable output performance.
SV00522
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ and nK to nCP set-up, the nCP to nJ, nK hold times and the maximum clock pulse frequency.
Vl nCP INPUT GND Vl nSD INPUT GND Vl nRD INPUT GND VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL VM VM tPHL tPLH tPLH VM tPHL VM tW trem tW trem VM
SV00523
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time.
1998 Apr 20
7
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 Apr 20
8
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 Apr 20
9
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 Apr 20
10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 Apr 20
11
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
74LV109
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04417
Philips Semiconductors
1998 Apr 20 12

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